This invention relates to a semiconductor integrated circuit including a redundancy circuit.
During the fabrication of semiconductor memories, there is a chance that one or more memory cells go defective. Some semiconductor memories feature a redundancy, including ordinary memory cells and redundant or spare memory cells. When an ordinary memory cell goes defective, the defective memory cell is replaced by a redundant (spare) memory cell. This replacement is executed by a redundancy circuit.
As will be explained later, a prior art semiconductor integrated circuit including a redundancy circuit has some problems.